Settings-Diff · BIOS Modifier Platform

ROM A (links) 9c37…9f85

Taichi

4.069 Settings · 152 VarStores

ROM B (rechts) 55d1…a46f

Taichi

4.068 Settings · 226 VarStores

Identisch

Geändert

unterschiedliche Defaults

Nur in A

Nur in B

Setting

VarStore : Offset

Wert A

Wert B

Kategorie

Forces CPU SoC/uncore components (e.g. Infinity Fabric, memory, and integrated graphics) to run at their maximum specified frequency at all times. May improve performance at the expense of idle power savings. On some products the ACPI sleep

AodSetupPhx:0x185

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RAS# to CAS# Delay to Write (tRCDWR)[1;37;m%d[;;m

Setup:0x1B5

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Row Precharge Time (tRP)[1;37;m%d[;;m

Setup:0x1B7

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RAS# Active Time (tRAS)[1;37;m%d[;;m

Setup:0x1B9

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RAS# Cycle Time (tRC)[1;37;m%d[;;m

Setup:0x1BB

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Write Recovery Time (tWR)[1;37;m%d[;;m

Setup:0x1BD

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Refresh Interval (tREFI)[1;37;m%d[;;m

Setup:0x1BF

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Refresh Cycle Time (tRFC1)[1;37;m%d[;;m

Setup:0x1C1

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Refresh Cycle Time (tRFC2)[1;37;m%d[;;m

Setup:0x1C3

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Refresh Cycle Time (tRFCSb)[1;37;m%d[;;m

Setup:0x1C5

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Read to Precharge (tRTP)[1;37;m%d[;;m

Setup:0x1C7

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RAS to RAS Delay (tRRD_L)[1;37;m%d[;;m

Setup:0x1C9

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RAS to RAS Delay (tRRD_S)[1;37;m%d[;;m

Setup:0x1CB

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Four Activate Window (tFAW)[1;37;m%d[;;m

Setup:0x1CD

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Write to Read Delay (tWTR_L)[1;37;m%d[;;m

Setup:0x1CF

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Write to Read Delay (tWTR_S)[1;37;m%d[;;m

Setup:0x1D1

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TrdrdScL[1;37;m%d[;;m

Setup:0x1D3

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TrdrdSc[1;37;m%d[;;m

Setup:0x1D5

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TrdrdSd[1;37;m%d[;;m

Setup:0x1D7

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TrdrdDd[1;37;m%d[;;m

Setup:0x1D9

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TwrwrScL[1;37;m%d[;;m

Setup:0x1DB

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TwrwrSc[1;37;m%d[;;m

Setup:0x1DD

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TwrwrSd[1;37;m%d[;;m

Setup:0x1DF

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{a1 #TwrwrDd{p200 #[1;37;m%d[;;m

Setup:0x1E1

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Twrrd[1;37;m%d[;;m

Setup:0x1E3

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Trdwr[1;37;m%d[;;m

Setup:0x1E5

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DFE Read Training

Setup:0x1E7

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Gear Down Mode

Setup:0x1E8

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Processor CA drive strengths[1;37;m%s[;;m

Setup:0x1E9

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Processor DQ drive strengths[1;37;m%s[;;m

Setup:0x1EA

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Processor ODT impedance[1;37;m%s[;;m

Setup:0x1EB

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Processor CS ODT impedance[1;37;m%s[;;m

Setup:0x1EC

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Processor CA ODT impedance[1;37;m%s[;;m

Setup:0x1ED

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Processor CK ODT impedance[1;37;m%s[;;m

Setup:0x1EE

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Processor DQ ODT impedance[1;37;m%s[;;m

Setup:0x1EF

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Processor DQS ODT impedance[1;37;m%s[;;m

Setup:0x1F0

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Dram DQ drive strengths[1;37;m%s[;;m

Setup:0x1F1

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Dram ODT impedance RTT_NOM_WR[1;37;m%s[;;m

Setup:0x1F2

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Dram ODT impedance RTT_NOM_RD[1;37;m%s[;;m

Setup:0x1F3

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Dram ODT impedance RTT_WR[1;37;m%s[;;m

Setup:0x1F4

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Dram ODT impedance RTT_PARK[1;37;m%s[;;m

Setup:0x1F5

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Dram ODT impedance DQS_RTT_PARK[1;37;m%s[;;m

Setup:0x1F6

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{w1300#VDDG CCD Voltage

Setup:0x1F8

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{w1300#VDDG IOD Voltage

Setup:0x1FA

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{w1300#VDDP Voltage

Setup:0x1FC

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{w1300#VDD Misc Voltage

Setup:0x1FE

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{w1430#VDDIO Voltage (VDDIO_MEM_S3)[1;37;m%d.%03dV[;;m

Setup:0x200

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{w1430# DRAM VDD Voltage

Setup:0x202

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{w1430# DRAM VDDQ Voltage

Setup:0x204

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{w1901# DRAM VPP Voltage

Setup:0x206

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Infinity Fabric Frequency

Setup:0x208

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DRAM Profile Setting

Setup:0x21B

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Runtime Reduction

Setup:0x21C

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Memory Slot Selection

Setup:0x21E

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Password Check

Setup:0x220

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Active Page on Entry

Setup:0x221

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SATA Mode

Setup:0x223

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SATA Port 1 Hot Plug

Setup:0x225

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SATA Port 2 Hot Plug

Setup:0x226

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SATA Port 3 Hot Plug

Setup:0x227

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SATA Port 4 Hot Plug

Setup:0x228

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Display Priority

Setup:0x23C

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Onboard Button LED

Setup:0x23E

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Red

Setup:0x245

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Blue

Setup:0x247

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PCIe Gen5 redriver

Setup:0x249

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Downstream High Frequency Peak Port A

Setup:0x24A

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Downstream High Frequency Peak Port B

Setup:0x24B

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Downstream Low Frequency Peak Port A

Setup:0x24C

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Downstream Low Frequency Peak Port B

Setup:0x24D

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Upstream High Frequency Peak Port A

Setup:0x24E

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Upstream High Frequency Peak Port B

Setup:0x24F

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Upstream Low Frequency Peak Port A

Setup:0x250

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Upstream Low Frequency Peak Port B

Setup:0x251

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